1. Field of the Invention
The present invention relates to a method for forming an isolation layer of a semiconductor device and the semiconductor device. More particularly, the present invention relates to a method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device.
2. Discussion of the Related Art
A conventional method for forming an isolation layer of a semiconductor device will be described with reference to the accompanying drawings.
Referring to FIGS. 1a through 1d, there is illustrated a conventional method for forming an isolation layer of a is semiconductor device. As shown in FIG. 1a, a first insulating layer 2 is formed on a semiconductor substrate 1, by a CVD process. In this case, the first insulating layer 2 has a thickness of 1 μm. The first insulating layer 2 is partially patterned by an RIE (reactive ion etching) process until a predetermined portion of the substrate 1 is exposed, thereby forming a contact hole. Next, a second insulating layer 3 of a thickness of 0.1 μm is formed on the entire surface inclusive of the exposed substrate 1 by the CVD process.
Subsequently, etch back is applied to the second insulating layer 3 so as to form a sidewall spacer 3a and then, the substrate 1 is etched by a predetermined depth with the first insulating layer 2 and the sidewall spacer 3a serving as masks, as shown in FIG. 1b. In this case, the substrate is etched by a width of 0.1 μm and a depth of 0.5 μm.
Next, the first insulating layer 2 and the sidewall spacer 3a, as shown in FIG. 1c, are removed to expose the surface of the substrate 1. Also, the surface of the substrate 1 is annealed for recovering the damage of the substrate 1 caused by the removal of the first insulating layer 2 and the sidewall spacer 3a, and there is grown an oxide layer 4 of a width of 200 Angstroms is grown on the entire surface of the substrate 1. After the growth, a third insulating layer 5 of a thickness of 3000 Angstroms is formed on the oxide layer 4 by the CVD process and then, a photoresist layer is coated on the third insulating layer 5. Subjected to exposure and development, the photoresist layer is patterned to form a photoresist pattern 6.
Referring to FIG. 1d, with the photoresist pattern 6 serving as a mask, the third insulating layer 5 is partially removed by the RIE process. After this removal, boron ions are implanted into the substrate three times; each time the boron ions have a different energy. In this case, the amount of boron ions is 3×1012 ions/cm2 and energies of the ions are 130 KeV, 180 KeV and 260 KeV.
The conventional method for forming an isolation layer of a semiconductor device has the following problems.
First, a semiconductor substrate may be impaired due to etch of an isolation region of the substrate. Further, since the isolation region is etched at a very steep slope angle, focus of charge currency is generated, thereby causing leakage current.
Second, when the isolation region is a large pattern, an etch width of the substrate 1 is increased so that the planarization of the surface of the isolation region becomes inferior.